The present invention relates to integrated circuits and a method of packaging integrated circuits and, more particularly, to stacked multi-chip package type integrated circuits.
An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer. Such a die is typically cut from the wafer and attached to a base carrier for interconnect redistribution. Bond pads on the die are then electrically connected to the leads on the carrier via wire bonding. The die and wire bonds are encapsulated with a protective material such that a package is formed. The leads encapsulated in the package are redistributed in a network of conductors within the carrier and end in an array of terminal points outside the package. Depending on the package types, these terminal points may be used as-is, such as in TSOP, or further processed, such as attaching spherical solder balls for a Ball Grid Array (BGA). The terminal points allow the die to be electrically connected with other circuits, such as on a printed circuit board. In subsequent examples, a MAPBGA is used to illustrate the invention disclosed herein.
With the goal of increasing the amount of circuitry in a package, but without increasing the area of the package so that the package does not take up any more space on the circuit board, manufacturers have been stacking two or more die within a single package. Such devices are sometimes referred to as stacked multichip packages. FIG. 1 shows a first conventional stacked multichip package 10. The package 10 includes a first or bottom die 12 attached to a base carrier 14 (in this example, a MAPBGA substrate) with a first adhesive layer 16. A second or top die 18 is attached to the bottom die 12 with a second adhesive layer 20 similar to the first adhesive layer 16. The bottom and top dice 12, 18 are electrically connected to the base carrier 14 with wires 22 and 24, respectively, via wirebonding. Terminals 26, in this case spherical solder ball terminals, are connected to a network or redistribution layer (not shown) of the base carrier 14. The bottom and top dice 12, 18 and the wires 22, 24 are sealed with a resin 28, thus forming the stacked multichip package 10. In order to allow the bottom die 12 to be wirebonded to the leads of the base carrier 14, the top die 18 must be smaller than the bottom die 12.
FIG. 2 shows a second conventional stacked multichip package 30. The second package 30 includes a first or bottom die 32 attached to a base carrier or substrate 34 with a first adhesive layer 36. Bond pads on the bottom die 32 are electrically connected to leads on the substrate 34 with first wires 38 via wirebonding. A spacer 40, typically made of bare silicon, is attached to the bottom die 32 with a second adhesive layer 42. A third or top die 44 is attached to the spacer 40 with a third adhesive layer 46.
The top die 44 is almost the same size or bigger than the bottom die 32. In such a situation, wirebonding of the bottom die 32 is impossible if the top and bottom dice 32, 44 are attached as shown in FIG. 1 (i.e., without the spacer 40). However, as shown in the drawing, the spacer 40 is smaller than the bottom die 32 so that the bottom die 32 may be wirebonded without obstruction. Thus, bond pads on the top die 44 are electrically connected to the substrate 34 with second wires 48 via wirebonding.
The total thickness of the spacer 40 and the second and third adhesive layers 42 and 46 must also be large enough so that the wires 38 connected to the bottom die 32 are not disturbed when the top die 44 is attached to the spacer 40. Spherical solder ball terminals 50 are connected to a wiring layer (not shown) of the substrate 34. The bottom die 32, top die 44, spacer 40 and the wires 38, 48 are sealed with a resin 52, thus forming the stacked multichip package 30. While this solution allows two die with almost the same size to be packaged together, the spacer 40 increases the process lead time, cost and size (height) of the package 30.
It would be desirable to be able to stack two or more die of the same size, or an even larger top die in a single package without unduly increasing the size of the resulting package and without the requirement of a spacer.